Small Spacing LED Display Bring Challenges To Led Chip

- May 15, 2019-

Compared with other display technologies, LED displays have the advantages of self-illumination, excellent color reproduction, high refresh rate, power saving and easy maintenance. High brightness and the ability to achieve very large sizes through splicing are the decisive factors for the rapid growth of led displays in the past two decades. In the field of outdoor display with large screen, there is no other technology that can compete with LED display technology.


However, in the past, led displays have also had their drawbacks, such as the large spacing between the encapsulated light beads, resulting in a low resolution, which is not suitable for indoor and close viewing. In order to improve the resolution, it is necessary to reduce the spacing between the light beads, but the size of the light beads is reduced, although it can improve the resolution of the whole screen, the cost will increase rapidly, too high cost affects the large-scale commercial application of small spacing led display.


In recent years, with the aid of chip manufacturing and packaging manufacturers, IC circuit manufacturers and the combined efforts of screen manufacturers such as single packaging device is lower and lower cost, LED packaging devices are getting smaller, display pixel pitch smaller and smaller, more and more high resolution, making small spacing LED display in indoor display advantages of more and more obvious.


At present, small spacing LED is mainly used in advertising media, sports venues, stage background, municipal engineering and other fields, and in transportation, broadcasting, military and other fields continue to develop the market. It is estimated that the market size will be close to 10 billion yuan in 2018. It can be predicted that in the next few years, the small spacing led display will continue to expand market share, and squeeze the DLP back projection market space. According to everbright securities research institute, by 2020, the replacement rate of small spacing led display to DLP will reach 70% to 80%.


The author is engaged in the blue and green LED chip manufacturing industry, engaged in product development work for many years. The following is from the perspective of product design, process technology to discuss the development of small spacing led display on the blue and green led chip requirements, and chip end may take countermeasures.


Second, small spacing led display on led chip requirements


As the core of led display, led chip plays a crucial role in the development of small spacing led. The current achievements and future development of small spacing led display depend on the unremitting efforts of chip terminal.


On the one hand, the point spacing of indoor display screen has been gradually reduced from P4 in the early stage to P1.5, P1.0 and P0.8 in the development stage. Correspondingly, the lamp bead size has been reduced from 3535 and 2121 to 1010. Some manufacturers have developed 0808 and 0606 sizes, and even some manufacturers are developing 0404 sizes.


As we all know, encapsulation lamp bead's size reduces, inevitably requests the chip size to reduce. At present, the surface area of blue and green chips commonly used in the market for small space displays is about 30mil2, and some chip factories have been mass producing chips of 25mil2 or even 20mil2.


On the other hand, with the decrease of chip surface area and single core brightness, a series of problems affecting display quality also become prominent.


The first is the requirement of gray scale. Different from outdoor screen, the difficulty of indoor screen demand is not in brightness but in grayscale. At present, the brightness requirement of indoor large-spacing screens is about 1500 CD/m2-2000 CD /m2, and the brightness of small-spacing led displays is generally around 600 CD/m2-800 CD /m2, while the optimal brightness of screens suitable for long-term attention is around 100 CD/m2-300 CD /m2.


At present, one of the difficulties of small spacing LED screen is "low light and low gray". That is, in low brightness under the grayscale is not enough. In order to realize "low light and high gray", black bracket is adopted at the packaging end. Due to the black stent on the chip of the light is weak, so the chip requires sufficient brightness.


Then there is the issue of display uniformity. Compared with the conventional screen, the smaller spacing will cause problems such as afterglow, the first sweep being dark, the low light being red and the low ash being uneven. At present, the packaging end and IC control end have made efforts to solve the problems of afterglow, first sweep and low gray color, which have been effectively alleviated. The problem of brightness uniformity under low gray level has also been alleviated through point-by-point correction technology. However, as one of the root causes of the problem, the chip side needs to pay more efforts. In particular, the small current brightness uniformity is better, better parasitic capacitance consistency.


The third is reliability. The current industry standard is that the allowable LED dead light rate is 1 in 10,000, which is obviously not applicable to small spacing LED displays. Due to the high pixel density of the small spacing screen and the close viewing distance, if there is one dead light for 10,000, the effect is unacceptable. The future dead light rate needs to be controlled at 1 in 100,000 or even 1 in 1 million to meet the demand of long-term use.


In general, with the development of small spacing LED, the requirements for chip segment are: smaller size, higher relative brightness, good brightness consistency of small current, good parasitic capacitance consistency and high reliability.


Third, the solution of chip terminal


1. Size reduction chip size reduction


On the surface, this is a layout problem that seems to be solved by designing smaller layouts as needed. But can chip reduction continue indefinitely? The answer is no. There are several reasons for the reduction of chip size:


(1) limitations of package processing. During package processing, two factors limit the reduction of chip size. One is the restriction of suction nozzle. The short side of the chip must be larger than the diameter of the nozzle. At present, the cost-effective suction nozzle inner diameter is about 80um. The second is the limitation of welding wire. Firstly, the welding wire coil, namely the chip electrode, must be large enough. Otherwise, the reliability of the welding wire cannot be guaranteed. The minimum electrode diameter reported in the industry is 45um. Second, the spacing between the electrodes must be large enough, otherwise the two welding lines will inevitably interfere with each other.


(2) restrictions on chip processing. There are also two limitations to chip processing. One is the limitation of layout. In addition to the limitations of the above package ends, electrode size and electrode spacing, the electrode distance from the MESA, the width of the trace, the boundary line spacing of different layers, etc., all have their limitations. The current characteristics of the chip, the processing capability of SD, and the processing capability of photolithography determine the specific limits. Normally, the minimum distance from the P electrode to the edge of the chip is limited to more than 14 m.


The other is the limitation of processing capacity. Both SD scribing and mechanical chip processes have their limits, and the chip size is too small to be split. As the diameter of a wafer increases from 2 inches to 4 inches, or in the future to 6 inches, the difficulty of scribing will increase, meaning that the size of the chip that can be machined will increase. In the case of a 4 "chip, if the short side length is less than 90 m and the aspect ratio is greater than 1.5:1, the yield loss will increase significantly.


Based on the above reasons, the author boldly predicted that after the chip size was reduced to 17mil2, the chip design and processing capacity approached the limit, and there was basically no room for reduction, unless there was a big breakthrough in chip technology solutions.


2. Brightness enhancement


Brightness enhancement is the eternal theme of chip terminal. The chip factory improves the internal quantum effect through the epitaxy optimization, and improves the external quantum effect through the chip structure adjustment.


However, on the one hand, the reduction of chip size will inevitably lead to the reduction of luminous area and the brightness of chip. On the other hand, the point-to-point spacing of the small-space displays is reduced, and the need for brightness of a single chip is reduced. There is a complementary relationship, but there is a bottom line. At present, in order to reduce the cost of chip, mainly in the structure of the subtraction, which usually pay the cost of brightness reduction, so how to balance the trade is the industry should pay attention to the problem.


3. Low current consistency


The so-called small current, is the conventional indoor, outdoor chip test current. As shown in the chip i-v curve below, conventional indoor and outdoor chips work in a linear working area with a large current. However, the LED chip with small spacing needs to work in a nonlinear working area close to 0, and the current is relatively small.


In the nonlinear workspace, LED chip is affected by the threshold value of semiconductor switch, and the difference between chips is more obvious. It is easy to see that the discretization of nonlinear working region is much larger than that of linear working region by analyzing the discretization of brightness and wavelength of large number of chips. This is an inherent challenge on the chip side at the moment.


The solution to this problem is the optimization of the epitaxial direction, mainly to reduce the lower limit of the linear workspace. The second is the optimization of the chip spectrophotometry, which can distinguish the chips with different characteristics.


4. Parasitic capacitor consistency


At present, there is no condition to measure the capacitance of the chip directly. The relationship between capacitance characteristics and conventional measurement items is not yet clear. The direction of chip end optimization is either epitaxial adjustment or electrical grading refinement, but the cost is very high and it is not recommended.


5. Reliability


The reliability of chip can be described by the parameters of chip package and aging process. But overall, the chip screen after the reliability of the impact factors, the focus on the ESD and IR two.


ESD is the ability to resist static electricity. According to IC industry reports, more than 50% of chip failures are related to ESD. To improve chip reliability, ESD capabilities must be enhanced. However, with the same epitaxial chip and chip structure, the reduction of chip size will inevitably weaken the ESD capability. This is directly related to the current density and capacitance characteristics of the chip, which is irresistible.


IR refers to reverse leakage, which is usually measured at a fixed reverse voltage to the reverse current value of the chip. IR reflects the number of internal defects in the chip. The higher the IR value, the more internal defects.


To improve the ESD capability and IR performance, more optimization must be made in the epitaxial structure and chip structure. In chip grading, strict grading standards can effectively eliminate chips with weak ESD capability and IR performance, so as to improve the reliability of on-screen chip.


Four,To sum up, the author analyzes the series of challenges faced by led chip terminal with the development of small spacing led display, and gives the improvement plan or direction one by one. Should say, current LED chip optimization still has very big space. How to improve, but also to play the wisdom of the unemployed, continuous efforts.